1. Field of the Invention
The invention relates to a method for fabricating metallic contacts, in particular bit-line contacts for an integrated circuit (IC), on a semiconductor wafer and to a memory cell having a metallic bit-line contact of this type, in particular for use in a dynamic random access memory (DRAM).
2. Description of the Related Art
Contact structures are formed in an insulator layer of a wafer with the aid of patterning methods and are then filled with a conducting material in order to make contact between electronic components in an integrated circuit (IC) on a semiconductor chip. Conducting material used are metals, metal alloys, doped semiconductors and electrically conductive organic substances. The various materials have different electrical properties. Contacts made from metals or metal alloys generally have the best electrical conductivity.
In dynamic memory chips, according to the current prior art, however, contact is made with semiconductor layers with the aid of metal contacts only at the peripheral substrate contacts in the peripheral circuit, and not in the memory cells themselves.
On account of the high integration density of DRAMs, bit-line contacts of the memory cells have very high aspect ratios with relatively small contact surface areas, which means that the introduction of uniform liner layers for the fabrication of metallic bit-line contacts is not practical in the memory cell array. However, liner layers of this type are required between the semiconductor substrate and the metal in order to prevent damage to the semiconductor substrate which may form during the deposition of the metal and the further heat treatment.
Furthermore, the structural elements which are defined directly in the region of the contact surface of a bit line react extremely sensitively to the process by which the bit-line contacts are fabricated. The doping of the semiconductor with foreign atoms, which is generally required when metals are used to make contact with semiconductor layers, in order to compensate for the different conduction band potentials of metal and semiconductor, causes considerable damage to the crystal lattice of the semiconductor substrate. This damage would impair the functioning of the memory cell and, in the worst possible scenario, would lead to the entire memory cell being destroyed.
In view of the above problems involved in the fabrication of metallic contacts, doped polysilicon, which does not require any particular matching to the semiconductor substrate and is particularly suitable for filling contact holes with a high aspect ratio, is customarily used to fill the bit-line contact holes.
In this fabrication method, which is referred to below as the polysilicon process, the bit-line structures are usually defined with the aid of the photolithography technique, in which first of all a photoresist layer is applied to the wafer surface, forming a mask for the subsequent etching of the insulator layer. Before deposition of a layer to fill the contact hole, the native oxide which collects in the contact hole as a constituent of the photolithographic layer has to be removed. The cleaning operation is usually carried out as wet chemical etching. The chemical substances used for this operation, in particular BHF, often also attack the insulator layer and lead to considerable widening of the defined contact hole structures, and consequently this process greatly increases the risk of short circuits between adjacent bit lines. To prevent these short circuits, therefore, the bit-line contacts are made smaller from the outset. However, this procedure considerable restricts the process window for etching of the bit-line contacts.
In the polysilicon process, the contact resistance of the bit-line contacts is determined to a very considerable extent by the doping of the polysilicon. In this process, the resistance of the bit-line contact can only be reduced by greater doping of the polysilicon, which in turn entails the risk of the dopant also diffusing out into the channel region of the select transistor, thus impairing functioning of the transistor. The risk of dopant diffusing out into the channel region also defines the minimum distance between the transistor electrodes and therefore limits the extent to which the bit-line contacts can be reduced in the polysilicon process.
U.S. Pat. No. 5,817,572 A, DE 199 52 273 A1 and U.S. Pat. No. 6,144,050 A have disclosed metallic contacts with a liner layer arranged between the metallic contact filling and an active region. On the other hand, DE 297 22 440 U1 discloses a semiconductor memory, the bit-line contacts of which have a metallic filling.